Propulsion control system cental processing unit board

ABSTRACT

For use in a propulsion control system, a microprocessor based central processing unit board includes both Multibus I and Multibus II interfaces. Multibus I master interface and Multibus slave interface controllers are designed for high data throughput by using programmed logic design (PLD) technology. In addition, the need for latching of data transceivers used in conventional Multibus I designs is eliminated. The Multibus II interface is removable.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 07/686,927, filed Apr. 18, 1991, now U.S. Pat. No. 5,377,356, granted Dec. 27, 1994, which was a continuation of application Ser. No. 07/584,933, filed Sep. 19, 1990, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of propulsion control system central processing unit (CPU) boards, and more particularly, to bus interface controller design in a CPU board in an Intel 80386 based propulsion control system for use with subway cars or the like.

2. Background Information

A propulsion control system for an advanced design subway car requires high-speed data acquisition, an ability to communicate with a host computer, and an ability to communicate to control slave input/output (I/O) boards for controlling servo systems of the subway car. These varied requirements have caused compromises in communications bus design in the past, and thus limited overall system performance and efficiency.

There are known a variety of buses, bus interfaces, and bus controllers in various microprocessor systems. One known industrial bus standard is the IEEE 796, or Multibus I, and another is the IEEE 1296, or Multibus II. "Multibus" is a trademark of the Intel Corporation for its unified bus architecture, which uses a single integrated bus for data, address and control information. The Intel Multibus is used, for example, for connecting random access memory (RAM), read only memory (ROM) and input/output (I/O) boards in a microprocessor based system. The Multibus carries five types of signals, including data, address, control, multilevel interrupt and timing signals. Modules connected to the bus act as either masters or slaves, masters having the ability to control the bus. Arbitration logic is provided for on the bus to handle requests from multiple bus masters. Data rates on the bus are a factor of the master and slave devices data rates. The Intel bus is configured with two connectors, the primary (P1) and the secondary (P2) connectors. P1 signals include the address, data, control and interrupt signals, as well as the power supply. Most of the signals on the bus operate with negative logic, i.e., they are true when low.

The Multibus I and Multibus II busses are both usable with Intel IAPX 86 CPU based systems, for instance an 80386 CPU based system. Various Multibus I and Multibus II interfaces are known. A device attached to a Multibus I interface has the capability to operate as a bus master and share a bus with other masters that reside on the bus. A device on the Multibus I interface also has the capacity to generate and receive both vectored and nonvectored interrupts as well as read/write references to input/output (I/O) and memory space. Because of the bus protocol used on the Multibus I, and other factors, it is suitable for communication with relatively slow slave I/O boards and the like. The Multibus II, on the other hand, allows interprocessor communications via message passing, and is suitable for high-speed communications.

In typical Multibus I designs, latching of data transceivers is required. Also, the existing devices, for instance the Intel 8288 and 8289 bus controller and arbiter respectively, limit the achievable data throughput of the bus system. Improved performance and a marriage of Multibus I and II capabilities in an integrated system are desirable.

Therefore, a propulsion control CPU board which overcomes the above limitations and provides system design flexibility by having both Multibus I and II interfaces on a single 80386 CPU board is proposed.

SUMMARY OF THE INVENTION

According to the present invention, the above described drawbacks and limitations existent in the field are overcome by providing a propulsion system CPU board containing both the Multibus I and the Multibus II interfaces. Higher data throughput is achieved by implementing the Multibus I (IEEE 796) control in programmed logic design (PLD) technology, and by elimination of the need for latching data transceivers.

It is therefore an object of the present invention to provide a Multibus I master interface, which when combined with an asynchronous slave interface, eliminates the need for latching transceivers used in conventional Multibus I designs.

It is a further object of the present invention to provide higher data throughput than achievable using typical devices, such as the Intel 8288 and 8289, by designing bus control in programmed logic (PLD) technology.

According to one aspect of the invention, a CPU board is provided with both the Multibus I and Multibus II interfaces. The Multibus II interface allows interprocessor communications via message passing. The Multibus I interface acts as a master and shares a bus with other masters residing thereon. The Multibus I receives both vectored and nonvectored interrupts and reads/writes references to I/O and memory space.

According to another aspect of the invention, the Multibus I master interface is designed using PLD technology facilitating higher data throughput.

According to another aspect of the invention, a novel Multibus I master interface is coupled with a novel Multibus I asynchronous slave interface, so as to eliminate the need for latching data transceivers used in typical Multibus I designs.

According to another aspect of the invention, the slave bus interface timing is controlled within a single PLD state machine device, allowing wait states to be added if required by changing only the state machine PLD. This allows the slave interface design to be usable over a wide range of I/O boards without requiring timing information on components before design implementation of the slave board can begin.

According to another aspect of the invention, the propulsion control CPU board is designed within a 160mm by 233.4mm format, allowing use in high vibration environments, such as exist in subway cars, and meets the industrial temperature range of -40° C. to +85° C.

When the propulsion control system slave CPU board of the present invention is used as an invertor controller, it will generate pulse patterns for firing the gate turn on (GTO) devices in a subway car control application.

These and other objects and aspects of the invention are better understood with reference to the detailed description and accompanying drawings, and it will be understood that changes in the specific structure shown and described may be made within the scope of the claims without departing from the spirit of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the major hardware components of an embodiment of the invention;

FIG. 2 is a functional black box diagram of a master bus (multibus I) control device according to an embodiment of the invention;

FIG. 3 is a state diagram for the master bus controller according to an embodiment of the invention;

FIG. 4 is a functional black box diagram of a multibus slave interface control device according to an embodiment of the invention;

FIG. 4A is a table listing for the multibus slave interface control device of FIG. 4 according to an embodiment of the invention;

FIG. 4B is a table listing test vector inputs and outputs for the device of FIG. 4;

FIG. 5 is a state diagram for the multibus slave interface face control device of FIG. 4;

FIGS. 6A to 6C are a schematic diagram of part of a slave bus interface according to an embodiment of the invention;

FIGS. 7A to 7F are a schematic diagram of part of a slave bus interface according to an embodiment of the invention;

FIG. 8 is a schematic diagram of part of a slave bus interface according to an embodiment of the invention;

FIG. 9 is a block diagram showing an example of a propulsion control system in which the invention may be practiced sown in block diagram form;

FIG. 10 is a block diagram showing an example of a propulsion logic signal flow diagram for a system in which the invention may be practiced;

FIGS. 11A and 11B are a schematic diagram of a Multibus I control logic according to an embodiment of the invention;

FIG. 12 is a timing diagram for read timing according to an embodiment of the invention;

FIG. 13 is a timing diagram for write timing according to an embodiment of the invention;

FIGS. 14A and 14B are a schematic diagram of a part of a Multibus II system illustrating the interconnect device and power PLD with pull-up resistors interconnected to the system and the removable feature according to one aspect of the invention;

FIG. 15 is a block diagram of a modified 80386 Multibus I Interface according to the invention;

FIG. 16 is a functional black box diagram of an embodiment of an arbiter Programmable Logic Device (PLD) (item 1101 in FIG. 11) according to an embodiment of the invention;

FIG. 17 is a table listing for the arbiter PLD of FIG. 16;

FIGS. 18 and 19 are table listings for the multibus control Programmable Logic Device (PLD) of FIGS. 2 and 3 (item 1102 in FIG. 11;

FIG. 20 is a functional black box diagram of an embodiment of a latch control PLD according to the invention;

FIG. 20A is a table listing for the latch controller PLD of FIG. 20 (item 1103 of FIG. 11);

FIGS. 20B and 20C are table listings for the latch control PLD of FIG. 20;

FIG. 21 is a functional black box diagram of an embodiment of a decoder PLD according to the invention;

FIG. 22 is the table listing for the decoder PLD of FIG. 21 (item 1103 in FIG. 11);

FIG. 23A is a functional black box diagram of an embodiment of an interrupt PLD according to the invention;

FIG, 23B is a listing of the specifications for the interrupt PLD of FIG, 23;

FIGS. 24A through 36D together comprise a schematic diagram of an embodiment of the propulsion control system CPU board of the present invention, wherein:

FIG. 24A to 24D are a schematic diagram which shows the 80386 CPU and its 80387 numeric compressor;

FIGS. 25A to 25C are a schematic diagram which shows the serial interface CPU board;

FIGS. 26A to 26D are the interconnection of the system with the Multibus I control logic PLD's shown here in more detail;

FIGS. 27A and 27B are a schematic diagram which shows the interconnection of the multifunction peripheral device with the system;

FIGS. 28A to 28C are a schematic diagram which shows read only memory (ROM) connected to the system;

FIGS. 29A and 29B are a schematic diagram which shows the interconnect device and power PLD with pull-up resistors interconnected to the system and the feature that allows for a removable Multibus II interface;

FIGS. 30A and 30B are a schematic diagram which shows random access memory (RAM) connected to the system;

FIGS. 31A to 31C are a schematic diagram which show buffers;

FIGS. 32A to 32C are a schematic diagram which shows the Multibus II control logic device, e.g., the message passing coprocessor;

FIGS. 33A to 33C are a schematic diagram which shows a connector;

FIGS. 34A to 34C are a schematic diagram which shows various system programmed logic devices (PLD's);

FIGS. 35A to 35C are a schematic diagram which shows a connector; and

FIGS. 36A to 36D are a schematic diagram showing the bypassing capacitors for the various devices;

FIG. 37A is a functional black box diagram of an embodiment of a power PLD according to the invention;

FIG. 37B is a table listing for the power PLD of FIG. 37A;

FIG. 38A is a functional black box diagram of an embodiment of a ready generator control memory PLD according to the invention;

FIG. 38B is a table listing for the ready generator control memory PLD of FIG. 38A;

FIG. 39A is a functional black box diagram of an embodiment of a ready generator control input/output (I/O) PLD according to the invention;

FIG. 39B is a table listing for the ready generator control I/O PLD of FIG. 39A;

FIG. 40A is a functional black box diagram of an embodiment of a read write timing generator control PLD according to the invention;

FIG. 40B is a table listing for the read write timing generator control PLD of FIG. 40A;

FIG. 41A is a functional black box diagram of an embodiment of an 80386 ready generator control PLD according to the invention;

FIG. 41B is a table listing for the 80386 ready generator control PLD of FIG. 41A;

FIG. 42A is a functional black box diagram of an embodiment of a ready system (RDYSYS) control PLD according to the invention; and

FIG. 42B is a table listing for the ready system (RDYSYS) control PLD of FIG. 42A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

System Overview

Referring to FIG. 1, shown is a block diagram of a microprocessor based propulsion control central processing unit board according to a preferred embodiment of the invention. The system components shown in FIG. 1 and their operation will now be described. The board is described later in more detail with respect to FIGS. 24A to 36D, which comprise a complete schematic for the preferred embodiment.

In the preferred embodiment, the microprocessor 100 is an Intel 80386 central processing unit (CPU). The 80386 CPU 100 (U50 in FIGS. 24A and 24B ) in this embodiment is fed a 40 MHz clock signal from clock 101. The CPU 100 is connected with an optional coprocessor 102 (U57 in. FIGS. 24C and 24D) in this embodiment. The coprocessor 102 is preferably an Intel 80387 math coprocessor or its equivalent, which is specifically designed to handle mathematically intensive data processing more efficiently than the CPU 100. The CPU 100 communicates with the rest of the system by means of control (CTL), address (ADDRESS) and data (DATA) lines as shown in simplified form. A buffer 104 and buffer control logic 103 serve to interface the CPU 100 to a local bus 106. Attached to this local bus 106, various system components are shown, including, for example, memory (RAM 105 and EPROMS 112) and data latch 111, and some special purpose devices. These may include the multifunction peripheral device 109 (U29 in FIGS. 27A and 27B) and serial interface 110 (U48 in FIG. 25C) as shown, which in a preferred embodiment are an Intel 82380 and 8530 respectively, or their equivalents.

The multifunction peripheral 109 connects to the local bus 106 via address and data lines and is fed by a clock 107 as shown. It receives and generates certain control signals, including generating interrupts to the Multibus I control logic 115, and receiving direct memory access (DMA) interrupts from the Multibus II message passing coprocessor 114, which in a preferred embodiment is an Intel MPC 82389 (U30 in FIGS. 32A and 32C), or its equivalent. The multifunction peripheral device 109 includes on-board a direct memory access controller, fifteen levels of interrupt, and a wait state generator. Local memory and input/output timing use the wait state generator. In this respect, it is used to control read and write strobe times by delaying the ready signal to the processor 100. The DMA function of the device 109 is used to control access to and from the 1296 BUS (Multibus II) 120 via the message passing coprocessor (CONTROL LOGIC) 114. The fifteen levels of interrupt in the device 109 are used to respond to interrupts generated by slave boards that may reside on the 796 BUS (Multibus I) 121.

The serial interface device 110 connects to the local bus 106 to send and receive data over data lines as shown, facilitating serial data communication with, for instance, a standard terminal device (not shown). The device may provide two serial channels.

The data latch 111 connects to the local bus 106 to receive data over data lines as shown.

The programmable read only memory (ROM) 112 and the random access memory (RAM) 105 attach to the local bus 106 with address and data lines as shown, for storage and retrieval of program instructions and data.

The Multibus II message passing coprocessor (CONTROL LOGIC) 114 is connected to the multifunction peripheral 109 as described above. Coprocessor 114 connects to an interconnect device 113, which in a preferred embodiment is an Intel 8751 microcontroller (U49 in FIG. 29B), or its equivalent, via control (CTL) and address/data lines (A/D). Coprocessor 114 is also connected to the Multibus II bus 120 (1296 BUS) via buffers 118 using address/data lines (A/D). Buffers 118 are also connected to the interconnect device 113 by control (CTL) lines. The Multibus II message passing coprocessor 114 is designed to function as a Multibus II controller. It has a bus interface and several transmit and receive FIFO's (first-in first-out registers) which are used to pass messages over the Multibus II bus. The interconnect device 113 provides a convenient way to augment the Multibus II message passing coprocessor 114 to interface with the Multibus II bus 120 and the rest of the system, described below.

The interconnect device 113 is connected to the Multibus II message passing coprocessor 114 and buffers 118 as described above. It is fed by an 11,059 MHz clock signal from clock 108. The interconnect device 113 receives signals from reset control logic 116, and outputs control signals to both the buffers 118 as earlier described, and to bus interface signal test light emitting diodes 117 (BIST LEDS), used for test and diagnostic purposes. Interconnect device 113 includes registers and programmable memory useful in interfacing the Multibus II message passing coprocessor 114. Interconnect device 113 provides what is known as "interconnect space." This interconnect space is implemented as an EPROM (electronically programmable read only memory) area where board identification information is stored. The interconnect device 113 also functions to disable the Multibus II interface devices (114, 118) and reset the processor 100 if the processor 100 does not write to the Multibus II control logic 114 within the first twenty seconds after power-up of the system as a fault check.

The reset control logic 116 causes the interconnect device 113 to reset the processor 100 as just described.

The bus interface signal test LED's 117 (BIST LEDS) are connected to receive control signals (CTL) from the interconnect device 113 for testing and diagnostic purposes as shown.

The Multibus I control logic 115 is comprised of several programmed logic devices in a preferred embodiment (shown in more detail in FIGS. 11A. 11B and 26A to 26D). These include a master bus controller PLD (U39, FIG. 2), an arbiter PLD (U61, FIG. 16), a decoder PLD (U35, FIG. 21) and a latch controller PLD (U36, FIG. 20 to 20C). The master bus controller PLD is described in detail below. The arbiter PLD, in cooperation with the rest of the preferred embodiment, essentially performs all of the functions that a conventional Intel 8289 performs, while the latch controller PLD, in cooperation with the rest of the preferred embodiment, essentially performs all of the functions that a conventional Intel 8288 performs. The control logic 115 receives signals (INTERRUPTS) from the multifunction peripheral device 109 and outputs control signals (CTL) to buffers 119 which connect to the Multibus I bus 121. These buffers 119 also connect to the local bus 106 via address and data lines. The Multibus I control logic 115 is composed of the programed logic devices (PLD's) mentioned above which perform, in cooperation with the rest of the preferred embodiment, the functions required of a Multibus I bus controller and arbiter in a superior manner than the conventional Intel 8288 and 8289 devices.

Master Controller U39

A master bus controller implemented as a program logic device (PLD), described as a state machine, according to a preferred embodiment of the invention is shown in FIG. 2 (also 1102 in FIG. 11A). For the master bus controller shown in FIG. 2, the signals labeled around the periphery thereof are set forth in the table below (see also FIG. 18). Numbers in parenthesis are pin numbers.

    ______________________________________                                         CLK (1)     40 MHz clock                                                       RDY386 (2)  Ready signal to '386 CPU                                           P2INT (3)   Multibus I interrupt                                               INT07 (4)   Multibus I interrupt request                                       MBCS (5)    Multibus I chip select                                             AEN (6)     Arbiter enable                                                     DC (7)      Data code control signal from CPU                                  ADS (8)     Address data strobe signal from CPU                                WR (9)      Write/read from signal from CPU                                    XACK (10)   Multibus I acknowledge                                             MIO (11)    Memory or Input/Output signal from CPU                             GND (12)    ground                                                             OEN (13)    output enable                                                      RDY380 (14) Ready signal from 82380                                            S5 (15)     State five                                                         S4 (16)     State four                                                         INTA (17)   Interrupt cycle active                                             S3 (18)     State three                                                        S2 (19)     State two                                                          S1 (20)     State one                                                          S0 (21)     State zero                                                         MBRDY (22)  Multibus ready                                                     RESET (23)  Processor reset                                                    VCC (24)    supply voltage                                                     ______________________________________                                    

The state diagram of a master bus controller according to the preferred embodiment of the invention is shown in FIG. 3 and listed in tabular form in FIG. 19. The master bus controller according to FIG. 3 has twelve states which define the sequence of its operation. The signals which cause a transition between the states are shown in FIG. 3, and are also listed in the table of FIG. 19.

Referring to FIG. 3, and beginning with state "A" the transitions between states in the preferred embodiment will now be described. The "!" is read as "NOT". As can be readily seen, the only transition paths out of state "A" are into states "B" and "M". The transition path logic is as follows: if (!ADS & !RESET) then go to state "M"; else if (!ADS & !MIO & !DC & !WR & !P2INT & !RESET) then go to state "B"; else stay in state "A". In other words, if the signals Address Data Strobe (ADS) and Processor reset (RESET) are negative, then transition to state "M" from state "A" will occur. And, if the signals Address Data strobe (ADS), Memory or input/output control signal from the CPU (MIO), Data code (DC), Write/read from CPU (WR), Multibus interrupt (P2INT), and Processor reset (RESET) are negative, then transition to state "B" from state "A" will occur. If neither of these if's occur, then there is no transition out of state "A". The first "if" corresponds to the Multibus cycle, and the second "if" to the interrupt (INTA) cycle.

The other state transitions proceed as shown in FIG. 3 and are tabulated in FIG. 19 in the same manner as described above, each transition path being defined by a set of signals causing the transition.

For instance, the transition from state "B" to state "D" corresponds to the Multibus write cycle. The transition from state "B" to state "C" corresponds to the Multibus read cycle. The transition from state "B" to state "F" corresponds to the first Multibus interrupt cycle. The transition back to state "A" from state "B"(and the other states) is a reset condition.

As can be determined from the table in FIG. 19, the remaining states and their corresponding activities or indications are listed below:

States M, N and O: (delay states three cycles before B)

State U: (end of first INTA cycle)

State G: (generate ready for end of first INTA cycle)

State I: (next or second INTA cycle started)

State Q: (goto A)

State E: (wait for ACK then end)

The master bus controller PLD is interconnected with the other PLD's which together make up the Multibus I control logic 115 as is shown in FIGS. 11A and 11B, and discussed in more detail below.

Slave bus interface

A functional black box diagram of a slave interface controller which connects to the Multibus I bus and is thereby controlled by the master according to a preferred embodiment of the invention is shown in FIG. 4. Definitions and test vector inputs and outputs are shown in tabular form FIGS. 4A and 4B, respectively. A state diagram of the preferred embodiment of a slave interface controller according to the invention is shown in FIG. 5. The signals which cause the transitions between states are shown in FIG. 5, in the same manner as for the master controller. The input signals (reference numbers in parenthesis) for the slave device shown in FIG. 4 are listed below:

    ______________________________________                                         CLK(1)      Clock                                                              BEN(2)      Board enable                                                       BWR(4)      Board write                                                        BRD(3)      Board read                                                         MYDECODE(5) This board selected                                                SPEN(6)     8259 acknowledge of interrupt                                      BINTA(7)    Board interrupt cycle                                              BRESET(8)   System reset signal from CPU or cntr logic                         ______________________________________                                    

The slave interface produces the following output signals:

    ______________________________________                                         DIR(23)            Direction                                                   STA(18)            Start                                                       XXACK(16)          Output complete                                             IOWR(15)           Write strobe                                                IORD(14)           Read strobe                                                 XEN(17)            Enable XXACK                                                ______________________________________                                    

The transitions between states for the slave controller are shown in tabular form in FIG. 4A and graphically depicted in FIG. 5, in the same manner as for the master controller.

FIGS. 6A to 6C, 7A to 7F and 8 are a schematic diagrams of a slave bus interface board implementation designed according to the invention. The board is designed to be a bus slave with interrupt support. The bus interface section is accessed via single even/double even byte transfers.

Referring to FIGS. 6A and 6B, the device 601 is used as a board address decoder. In the preferred embodiment, it is implemented as a programmed logic device (PLD). When the output pin 603 (22) goes low, the board is selected. The slave board is designed to reside at one of four sets of locations depending on the positions of the jumpers jpr1 & jpr2. This method of board decoding was chosen so that on jobs which require more than one slave board, the boards can be interchanged easily without having to make any firmware changes.

Device 602 is used to buffer several control bus signals from the master that are used on the board. In the preferred embodiment, this device is a 54FCT244 or equivalent. The memory read and write signals (MRDC & IORC) (MWTC & IOWC), bus clock (BCLK), and the reset (INIT) signals are buffered by this device. The device also buffers the interrupt acknowledge signal (INTA). The Multibus I acknowledge (XACK) is not buffered as can be seen.

Devices 604, 605, 606 and 607 are used to generate the board enable signal (BEN) 608 which indicates this board is being accessed by the present bus cycle. Two levels of D-type flip-flops are necessary to synchronize them with the 10 MHz timing clock. The signal BEN 608 is kept high by feeding the inverted output of device 607 pin 10 back to the PRESET pin. Device 605 is used to NAND together the read and write strobes. The output of device 605 is then fed to the clear line of device 607 (pin 13). This will remove the BEN signal 608 once the read or write strobe goes away. By using the read or write strobe to clear the BEN signal 608, it is ensured that all the bus cycles are received.

Device 609 is the slave control programmed logic device (PLD) in a preferred embodiment as was described with reference to FIGS. 4, 4A, 4B and 5 above. Device 609 has ten registered outputs, several of which are used to form a mode state machine (S0, S1, S2, S3, S4) which is clocked by the rising edges of a 10 MHz timing reference. The on-board control signals (DIR, STA, XACK, IOWR, IORD) are produced at the remaining five outputs. Eight of the device's pins are used to input control signals. The slave control logic 609 generates the timing read and write strobes for the slave board only. When the read or write is completed, it drives the XACK line to signal the master that it has finished.

Referring now to FIGS. 7A to 7F, device 701 is used to buffer, invert and latch some of the address lines used. Devices 702 and 703 are data buffers and are enabled/disabled by the signal BEN 608 or SP/EN. FIG. 8 is more of the slave controller circuitry, showing the interrupt generating circuit which generates interrupt signals for the bus.

Referring now to FIGS. 9 and 10, shown in block diagram form is a propulsion control system and a propulsion logic signal flow diagram, respectively, which illustrate a system in which the propulsion control system central processing unit board of the present invention is used. Various signals are used by the propulsion control system to control the operation of a subway car.

Referring now to FIGS. 11A and 11B, the master bus controller U39 described above (item 1102) is shown connected to the other PLD's (1101, 1103, 1104) which comprise the Multibus I master control logic 115 in an embodiment of the invention. PLD 1101 is the arbiter, PLD 1103 is the latch controller and PLD 1104 is the decoder. The arbiter PLD performs the functions that a conventional Intel 8289 or its equivalent performs, while the latch controller PLD performs the functions that a conventional Intel 8288 or its equivalent performs. Decoder PLD 1104 decodes input signals to produce the signal 1105 which corresponds to the Multibus I chip select (MBCS) signal fed to the master bus controller 1102 and arbiter 1101.

Referring to FIGS. 12 and 13, shown is a timing diagram for read timing in FIG. 12, and FIG. 13 shows a timing diagram for write timing for the CPU board, according to the present invention.

Referring now to FIGS. 14A and 14B, shown is a circuit diagram of the removable Multibus II feature according to one aspect of the invention. The Multibus II interface resident on the board may not be required for all applications and has been designed to be removable with this in mind. As described in more detail later, certain support circuitry is required if the Multibus II interface is removed. FIGS. 14A and 14B show the interconnect device U49 (113) and power PLD U24 with pull-up resistors interconnected to the system.

Referring now to FIG. 15, shown is a block diagram of an embodiment of a modified architecture of an 80386 Multibus I Interface according to the invention, showing how PLD's 1101, 1102, 1103 and 1104 replace and expand the capabilites over conventional devices and architecture to form the Multibus I control logic 115 of FIG. 1.

Referring now to FIGS. 16 and 17, arbiter PLD U61 (1101) is shown and specified in tabular form, including the state equations and pin definitions, respectively. In the preferred embodiment, the device performs the multibus arbiter function as described above.

Referring now to FIGS. 18 and 19, listed are the specifications for a preferred embodiment of the master controller PLD U39 (1102), described above with respect to FIGS. 2, 3 and 11A to 11B, including the state equations and pin definitions.

Referring now to FIGS. 20, 20A, 20B and 20C, shown and listed in tabular form is a preferred embodiment of the latch controller PLD U36 (1103) and its specifications, including equations and pin definitions, and test vectors in two parts, respectively, described above with respect to FIGS. 11A to 11B.

Referring now to FIGS. 21 and 22, shown is a preferred embodiment of the decoder PLD U35 (1104), described with respect to FIGS. 11A to 11B above, and its specifications, including its equations and pin definitions, respectively.

Referring now to FIGS. 23A and 23B, shown is a preferred embodiment of the interrupt PLD U56 (see FIGS. 26A to 26D), and its definitions, including the state equations and pin definitions, respectively, for use with the propulsion control system CPU board according to the invention.

FIGS. 24A through 36D together comprise a complete schematic for a preferred embodiment of the propulsion control system CPU board of the present invention. Highlights of some of the significant features in the figures are now described. FIGS. 24A to 24D show the 80386 CPU (U50) and its 80387 numeric coprocessor (U57) interconnected. FIGS. 25A to 25C show the 8530 serial interface (U48) connected to jacks (J3 and J4) via drivers (U31 and U41), and show associated address and data latches (U44, U46, U51, U53, U55, U58, U60 and U62). FIGS. 26A to 25C show shows the interconnection of the system with the Multibus I control logic PLD's (U35, U36, U39 and U61), shown in simplified form in FIGS. 11A and 11B, show here in more detail and interconnected with the system. FIGS. 27A and 27B show the interconnection of the 82380 multifunction peripheral device U29 (109) with the system. FIGS. 28A to 28C show read only memory U1-U4 (ROM) connected to the system. FIGS. 29A and 29B show the 8751 interconnect device U49 (113) and power PLD U24 with pull-up resistors interconnected to the system. This arrangement allows for a removable Multibus II interface.

FIGS. 14A 14B and FIGS. 32A to 32C show the components that make up the Multibus II interface. The Multibus II interface will not be required in all applications. If the Multibus II is required, all system support functions are provided via the Multibus II interface control logic 114 (U30). If an application doesn't require the interface, additional support circuitry must be added. Device U20 provides power-up, watchdog timer and reset functions. PLD U24 is programmed to accept voltage-low input conditions, power-up reset timing inputs from the Multibus II interface control logic 114 (U30) or device U20. The 8751 microcontroller 113 (U49) provides support for interconnect space and can be removed without additional support circuitry with the exception of several pull-up resistors. All signals that interface from devices U49 (e.g. REST1, REDLED) and U12 (e.g. BCLK, PSBRST and DCLOW) to PLD U24 are pulled high via 10k or 20k pull-up resistors. The use of pull-up resistors permits the use of the same PLD equations in both applications. Using PLD U24 allows the removal of U49, U12, U30 and the Bus line drivers.

FIGS. 30A and 30B show random access memory (RAM) U14-U17 connected to the system. FIGS. 31A to 31C show buffers connected to the system. FIGS. 32A to 32C show the 82389 Multibus II control logic device U30 (114), the message passing coprocessor, interconnected to the system. FIGS. 33A to 33C and 35A to 35C show bus connectors P1 and P2.

FIGS. 34A to 34C show various system programmed logic devices (PLD's) U25 Memory PLD, U26 I/O PLD, U27 CNTR PLD, U28 RDY PLD, and U32 RDY SYC. These PLD's are shown individually in FIGS. 38A, 39A, 40A, 41A and 42A, respectively, and the specifications for these PLD's are provided in tabular form in FIGS. 38B, 39B, 40B, 41B and 42B, respectively. FIGS. 36A to 36D show the bypassing capacitors for the various devices.

FIGS. 37A and 37B show a preferred embodiment of the power PLD U24 and its specifications, including equations and pin definitions. FIGS. 38A and 38B show a preferred embodiment of the memory PLD U25 and its specifications, including equations and pin definitions. FIGS. 39A and 39B show a preferred embodiment of the I/O PLD U26 and its specifications, including equations, test vectors and pin definitions. FIGS. 40A and 40B show a preferred embodiment of the read/write timing generator (CNTR PLD) PLD U27 and its specifications, including equations and pin definitions. FIGS. 41A and 41B show a preferred embodiment of the RDY PLD U28 and its specifications, including equations, test vectors and pin definitions. And FIGS. 42A and 42B show a preferred embodiment of the RDY SYC PLD U32 and its specifications, including equations and pin definitions.

It will be apparent to one of ordinary skill in the art that the manner of making and using the claimed invention has been adequately disclosed in the above written description of the preferred embodiment taken together with the drawings.

It will be understood that the above description of the preferred embodiment of the present invention is susceptible to various modifications, changes, and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims. 

I claim:
 1. A propulsion control system for controlling a vehicle, said propulsion control system comprising:a field connector interface board connected to vehicle wiring; a plurality of master and slave interface and control boards connected to the field connector interface board, said plurality of master and slave interface and control boards including a digital input-output board, an analog input-output board, a bitbus board, a tach reader board, a memory board, and a master CPU board, each of which are connected to the field connector interface board; a first bus connected to the plurality of master and slave interface and control boards and a second bus connected to the master CPU board; wherein, the master CPU board comprises:a local bus; memory; a multifunction peripheral device; and a central processing unit operatively connected to said memory and said multifunction peripheral device by said local bus, with said multifunction peripheral device including:wait state generator means for generating timing signals, direct memory access control means for controlling data transfer in said system, and interrupt handling means for generating interrupt requests and handling direct memory access interrupts; a first bus interface, operatively connected to said multifunction peripheral device and said local bus, including: first bus master control logic means for controlling the first bus responsive to said interrupt requests from said interrupt handling means; and buffering means for buffering data between said local bus and the first bus responsive to said first bus control logic means; and a second bus interface, operatively connected to said multifunction peripheral device, including: second bus master control logic means for controlling the second bus and producing said direct memory access interrupts; interconnect means for interfacing control signals from said second bus control logic means; reset control having an output connected to said interconnect means; and buffering means for buffering data between the second bus and said second bus control logic means responsive to control signals from said interconnect means; with said central processing unit circuit board communicating with the remaining components of said propulsion control system via said first and said second buses.
 2. The propulsion control system according to claim 1, wherein said first bus master control logic means for controlling the first bus comprises:bus control logic means for producing timing and control signals; arbiter means, responsive to said timing and control signals, for providing bus protocol control and synchronization of the central processor with the first bus; decoder means, responsive to said timing and control signals, for enabling said bus control logic means responsive to address signals from the central processor; and latch control means, responsive to said timing and control signals, for generating command and control timing for the first bus to optimize its performance. 